It is well known that semiconductor junctions and especially the gate oxides of MOS transistors are easily damaged by reason of electrostatic discharge (ESD). The silicon dioxide (SiO.sub.2) gate insulators typically have a thickness on the order of about 400 Angstroms. Breakdown potentials are on the order of from 20 to 50 volts. Where one or more pins of the device are exposed to an electrostatic potential which differs from the electrostatic potential already thereon, the ensuing discharge of energy may cause permanent damage to the input circuit of the device, either by excessive current density in avalanche breakdown, by gate oxide rupture or by gradual degradation due to the cumulative trapping of charges in the gate insulator. The capability of the device to withstand that discharge of energy may be quantified by means of an ESD test.
In such an ESD test, a capacitor, simulating the capacitance of the human body, is charged from a voltage supply to a predetermined voltage and then is discharged into the input pin of the device under test through a mercury wetted contact and a series current limiting resistor. Generally, the resistance value of such a resistor is in the range of between zero and 1500 ohms and the voltage supply may be on the order of from 500 to 2000 volts.
After such discharge, the device under test is checked for leakage at an applied voltage, representing a working voltage of, for example, five volts. The leakage in an undamaged device would not be expected to be more than, for example, one microampere. Typically, for an ESD test of this nature, U.S. industry standards would require the use of a 100 pF test capacitor discharged through mercury wetted contacts and a 1500 ohm series limiting resistor into the device input circuit pin or pad.
By accepted definition in this industry, a poorly protected MOS input circuit would be damaged by a potential of about 700 volts, an acceptable input circuit network would protect to potentials up to approximately 1500 volts and an input circuit considered to be very good would protect against potentials up to about 3000 volts. Because test equipment is not generally available to provide a 3000 volt test, it is common practice to provide, instead, a 200 pF test capacitor and, in that case, the aforementioned very good protective circuit might withstand 2000 volts or more.
In the past, the failure mechanism of greatest concern was rupture of the gate insulating oxide of the MOS device. This rupture occurred at approximately 50 volts with practically no current flow required. As a result, input circuits are commonly used which employ an RC network and/or some sort of gate clamping device; a gated diode or a field inversion transistor, either of which protects the MOS gate by breaking down in an avalanche mode or in the case of field inversion transistor by source/drain turn-on. In that case, failures are usually traced to a fatal failure of the protection circuit rather than the MOS device input gate. However, such catastropic failures in the input protection network are just as fatal to the device as a failure in the gate oxide insulator.
To illustrate the harsh conditions which prevail in MOS devices, one has only to consider that the input breakdown occurs in a normal MOS integrated circuit at between approximately 20 volts and 50 volts; the 20 volt failure threshold being a function of the gated diode or polysilicon field inversion transistor and the 50 volt failure threshold occurring in the N+/P junction of the MOS device. These breakdowns demonstrate a very low resistance for voltages higher than the threshold breakdown voltage of the protective circuit. Additionally, the high density breakdown current leads to secondary effects such as bipolar transistor action which further lowers the breakdown resistance.
It can be assumed, as a crude estimate, that the voltage at the input pin of the device under test is clamped at between 50 and 100 volts by the protective circuit. At the input side of the 1500 ohm series test resistor, the voltage, for good input protection, must be assumed to be equal to or more than 2000 volts. Hence, a conservative estimate of the momentary maximum current into the input pin is on the order of: EQU (2000-100)V/1500.OMEGA.=1.26 amperes.
Ideally, the specification for input protection should be set at the maximum voltage which could be applied prior to damage of the input circuit. Of course, the size of the test capacitor and series current limiting resistor must also be specified. Depending upon the specific protection circuit, the damage is caused either by the maximum (momentary) current density or by the total energy/charge dissipated, or by a combination of both. It is clear that the peak current density is controlled by the value of the series limiting resistor (whether part of the test circuit or internal to the chip); varying the capacitor voltage controls both peak current density and total dissipated energy, while variation of the capacitor size affects changes in the total energy only.
Thus it may be seen that by testing for the destructive limits of a given input protection circuit as a function of all three boundary conditions; capacitor voltage, capacitor value and series resistance; one can assess which of the failure modes is dominant. For example, if there is evidence of electromigration, the failure is probably due to excessive peak current density; if there is evidence of junction fusing by way of excessive joule heating of the junction, the failure is probably due to excessive total energy dissipated.
It must be noted that ESD occurs within approximately 100 nanoseconds of its application and that damage occurs within the first fractions of a nanosecond. Thus, due to the extremely fast rise times, even test fixture lead inductance has an effect on the test results. Additionally, it is difficult to predict the resistance values of the protection network and of the external wiring because of the skin effect due to fast rise times. It is clear that testing must be carefully controlled.
With 2000 volts or more at the input pin, avalanche breakdown is inevitable. The objective of an input protection circuit is not avoidance of the breakdown, but rather, survival of both the input gate oxide insulation and the protective circuit, without permanent damage to either. Avalanche breakdown is generally characterized by a negative temperature coefficient. In any preferred current (low resistance) path caused by the avalanche, high current density occurs. This creates a "hot spot" and the avalanche effect in the hot spot is increased even more by the positive feedback current characteristic due to the negative temperature coefficient; all of which causes still higher current and current density through the hot spot. The phenomena is well known as "thermal runaway". Excessive current density and/or temperature results in permanent damage in the hot spot.
Metal contact to silicon is made by depositing aluminum at elevated temperatures and alloying it with the silicon during subsequent heat treatment in a forming gas. The contact interface between silicon and aluminum is not planar, but rather, silicon is dissolved into aluminum at the interface and aluminum fills the voids left by the diffused silicon. These filled voids may be in the nature of metal spikes of aluminum which partially penetrate the N+ diffusion layer. In the worst case, the spike will extend all the way through the junction and create a short circuit to the P- substrate. (The aluminum, which is a P dopant, makes direct ohmic contact with the P- substrate and shorts the input to the substrate.) But even where the spike does not reach all the way to the substrate, the metal spike establishes a preferred current path deep in the diffusion layer and breakdown occurs from that point, in the path of lowest resistance. As the diffused layer is reduced in depth, this "spiking" effect is increased. Furthermore, with the increasing development of very large scale integrated circuits (VLSI), semiconductor junctions and gate insulations have become increasingly shallow in depth.
Where metal and buried contacts are configured with square or hard corners or with convex "points", there is a high electric field in these corners and this establishes a preferred path for breakdown which, in turn, results in a very high current density in those corners. The high voltage from the input pad, coming through the metal, metal contact, down through the polycrystalline silicon (as it is used in the instant invention, see the description, infra) sees an N+ diffusion. This N+ diffusion is the first place where the high voltage is clamped by avalanche breakdown and it is the first place on the semiconductor chip where significant energy is dissipated. The side wall junction has a steeper gradient and thus a lower breakdown voltage than the bottom junction since the sides of the N+ diffusion touch a boron channel stop field implant.
In addition, there is an electric field enhancement by reason of the curvature of the perimeter of the junction. As the radius of the junction is reduced, the electric field becomes higher for the same input potential. With a rectangular diffusion shape, the junction has a three dimensional corner close to the bottom of the junction in the corner of the shape, and at that point the junction gradient is still higher than at the bottom or side of the N+ diffusion. This creates another preferred path for breakdown current during avalanche and practically all of the electrostatic discharge current goes through these corners. This results in the maximum safe current density being exceeded in the ensuing hot spot at a lower input potential.